One of the most important factors in the performance of a high speed, sophisticated computer is the performance of the associated memory system. It is now generally assumed that such a computer system will include the use of a cache memory to facilitate the handling of program requested information. It is known that the larger the capacity and the faster the speed of operation of a cache memory, the better the overall performance of the computer system.
The prior art shows various efforts to improve the performance of cache memories. These efforts have included the use of multiple cache memories in various organizational relationships. For example, the use of separate cache memories for instructions and for data is known. Other cache designs use two caches in parallel in an odd-even interleave design so that memory access time for information from the cache for a string of data is improved. Other cache designs use different size caches in a hierarchical arrangement. Some of these cache designs are intended for use with more than one processing element or execution unit so that several different cache accesses may be initiated in a short time interval.
One of the difficulties typical of these prior art designs is that when a cache request is made, the cache must perform a search to determine if the information is available. If the cache access is successful, the information is provided to the requesting unit. If the information is not available, a cache miss signal is followed which summons the requested information from another level of memory while the requesting unit either waits or does something else. In most cache designs there is a significant time penalty if a cache miss occurs and the design is optimized so that cache misses are infrequent.
Applicant is aware of the following pertinent patents and publications:
U.S. Pat. No. 4,169,284 entitled "Cache Control For Concurrent Access", assigned to the same assignee as the present invention, shows a cache memory control which provides two cache access timing cycles during each processor storage request cycle. Although this cache allows more than one access per cycle it represents a time interleaved cache and not a true simultaneous access cache.
U.S. Pat. No. 4,371,929 entitled "Multiprocessor System with High Density Memory Set Architecture Including Partitionable Cache Store Interface To Shared Disk Drive Memory", assigned to the same assignee as the present invention, shows a cache memory with storage partitions functioning on a time interleaved basis.
U.S. Pat. No. 4,441,155 entitled "Page Controlled Cache Directory Addressing", assigned to the same assignee as the present invention, shows a cache addressing control system to reduce the cache miss rate.
U.S. Pat. No. 4,442,487 entitled "Three Level Memory Hierarchy Using Write And Share Flags", assigned to the same assignee as the present invention, shows different levels of cache and cache separated into private and shared cache systems. The private and shared cache systems are primarily separate caches with switching mechanisms between them and are not separate portions of the same cache. This design is intended to allow multiprocessor systems to share a memory facility without having the cross-interrogation requirements that would otherwise be necessary.
U.S. Pat. No. 4,463,424 entitled "Method For Dynamically Allocating LRU/MRU Managed Memory Among Concurrent Sequential Processes", assigned to the same assignee as the present invention, is a cache management system for separating a cache memory into partitions of allocated space based on the requirement of the process using the cache memory. The partitions are allocated by a supervisory process and are not physically determined.
U.S. Pat. No. 4,464,712 entitled "Second Level Cache Replacement Method and Apparatus", assigned to the same assignee as the present invention, treats a cache memory system as consisting of separate subsets of pages which are associated with a replacement flag mechanism to control access for replacement of cache contents.
U.S. Pat. No. 4,484,267 entitled "Cache Sharing Control In A Multiprocessor" assigned to the same assignee as the present invention, is a multiprocessing environment where each processor has a private cache. Each cache has a directory containing a sharing flag to control whether the associated cache line operates in a store-through of a store-in mode. This creates two different types of cache operating modes for use in handling both normal cache accesses and the cross-interrogation process with other caches.
There are other patents of interest in this field. U.S. Pat. No. 4,503,501 shows cache memory space partitioned into domains by a supervisory control system. U.S. Pat. No. 4,493,033 shows a dual ported cache operating in a time interleaved manner. U.S. Pat. No. 4,195,342 shows another dual ported interleaved cache arrangement. U.S. Pat. No. 3,618,041 is an early patent showing segregation of instructions and operands into different caches. U.S. Pat. No. 4,502,110 is a split cache having equal size operand and instruction memories.
IBM Technical Disclosure Bulletin, Vol. 22, No. 2, July 1979, pages 851 and 852, entitled "Partitioned Memory And Split SCE For Asymmetric Multiprocessor" shows an electronic fence under supervisory control for separating a memory into two sections and restricting access to one of the two sections.
U.S. Pat. No. 4,797,814 entitled "Variable Address Mode Cache" by J. G. Brenza and having the same inventorship and assignee as the subject application has important background information for the subject application. The contents of U.S. Pat. No. 4,797,814 are incorporated by reference into the subject application.
There is a continuing need for improvements in cache memory design, particularly for cache designs that may be used to handle a large number of requests in a short time interval or essentially simultaneously.